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Differential D4801 Diff 21129 ps/trunk/libraries/source/nvtt/src/src/nvthread/Atomic.h

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ps/trunk/libraries/source/nvtt/src/src/nvthread/Atomic.h

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesnamespace nv {
// Load and stores. // Load and stores.
inline uint32 loadRelaxed(const uint32 * ptr) { return *ptr; } inline uint32 loadRelaxed(const uint32 * ptr) { return *ptr; }
inline void storeRelaxed(uint32 * ptr, uint32 value) { *ptr = value; } inline void storeRelaxed(uint32 * ptr, uint32 value) { *ptr = value; }
inline uint32 loadAcquire(const volatile uint32 * ptr) inline uint32 loadAcquire(const volatile uint32 * ptr)
{ {
nvDebugCheck((intptr_t(ptr) & 3) == 0); nvDebugCheck((intptr_t(ptr) & 3) == 0);
#if POSH_CPU_X86 || POSH_CPU_X86_64 #if POSH_CPU_X86 || POSH_CPU_X86_64 || POSH_CPU_E2K
uint32 ret = *ptr; // on x86, loads are Acquire uint32 ret = *ptr; // on x86, loads are Acquire
nvCompilerReadBarrier(); nvCompilerReadBarrier();
return ret; return ret;
#elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64 #elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64
// need more specific cpu type for armv7? // need more specific cpu type for armv7?
// also utilizes a full barrier // also utilizes a full barrier
// currently treating laod like x86 - this could be wrong // currently treating laod like x86 - this could be wrong
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#endif #endif
} }
inline void storeRelease(volatile uint32 * ptr, uint32 value) inline void storeRelease(volatile uint32 * ptr, uint32 value)
{ {
nvDebugCheck((intptr_t(ptr) & 3) == 0); nvDebugCheck((intptr_t(ptr) & 3) == 0);
nvDebugCheck((intptr_t(&value) & 3) == 0); nvDebugCheck((intptr_t(&value) & 3) == 0);
#if POSH_CPU_X86 || POSH_CPU_X86_64 #if POSH_CPU_X86 || POSH_CPU_X86_64 || POSH_CPU_E2K
nvCompilerWriteBarrier(); nvCompilerWriteBarrier();
*ptr = value; // on x86, stores are Release *ptr = value; // on x86, stores are Release
//nvCompilerWriteBarrier(); // @@ IC: Where does this barrier go? In nvtt it was after, in Witness before. Not sure which one is right. //nvCompilerWriteBarrier(); // @@ IC: Where does this barrier go? In nvtt it was after, in Witness before. Not sure which one is right.
#elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64 #elif POSH_CPU_STRONGARM || POSH_CPU_AARCH64
// this is the easiest but slowest way to do this // this is the easiest but slowest way to do this
nvCompilerReadWriteBarrier(); nvCompilerReadWriteBarrier();
*ptr = value; //strex? *ptr = value; //strex?
nvCompilerReadWriteBarrier(); nvCompilerReadWriteBarrier();
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